The present invention relates to a semiconductor memory device wherein a data storage circuit including a memory cell and an error correction circuit for correcting error data caused by soft errors are formed on a single semiconductor chip and, more particularly, to a semiconductor memory device with an error correction function used in a computer which can reliably prevent storage of data errors.
Semiconductor memory devices with a function for detecting erroneous data storage and correcting the detected errors have not yet been mass-produced. Currently, the only such semiconductor memory devices are test samples. These devices detect and correct data errors in accordance with various methods. Basically, each device comprises one or more redundant-bit memory cells in addition to a given number of memory cells. In a data write mode, error correction data calculated by a given rule is written in advance not only in a memory cell group for storing normal data but also in the redundant-bit memory cell. Furthermore, in a data read mode, storage data in the memory cell group corresponding to an input address and in the redundant-bit memory cell arranged corresponding thereto are read out therefrom and checked. If no error occurs in the storage data in the memory cell group, the data is output without being modified, and if an error occurs, the data is corrected and then output.
Such a conventional semiconductor memory device has the following drawbacks.
First, such a method for checking memory cell for storage data errors in the data read mode only degrades reliability. In this method, in a memory cell which has not been subjected to a data readout operation for a long period of time after the data was written therein, data errors occur increasingly often. Therefore, data errors easily occur in more memory cells than the number of bits which can be corrected by an error correction circuit.
A second drawback of the conventional memory device is prolonged data write/read period. In the data write mode, data is written in normal data storage memory cells, and at the same time, error correction data calculated by a correction circuit must be written in the redundant-bit memory cell in the identical word block. Furthermore, in the data read mode, data respectively read out from the memory cell group and the redundant-bit memory cell are checked by a decoder. If error data is found, it must be corrected by the correction circuit. Thus, extra time in the data read/write modes prevents realization of high-speed computers.